1. Field of the Invention
The present disclosure relates to complex semiconductor devices of the SOI type, and, more particularly, to semiconductor devices of the SOI type with source/drain regions having different height levels, and methods of forming according semiconductor devices.
2. Description of the Related Art
In modern electronic equipment, integrated circuits (ICs) experience a vast applicability in a continuously spreading range of applications. In particular, the demand for increasing mobility of electronic devices at high performance and low energy consumption drives developments to more and more compact devices having features with sizes significantly smaller than 1 μm, the more so as current semiconductor technologies are apt of producing structures with dimensions in the magnitude of 100 nm or less. With ICs representing a set of electronic circuit elements integrated on a semiconductor material, normally silicon, ICs may be made much smaller than any discreet circuit composed of separate independent circuit components. Indeed, the majority of present-day ICs are implemented by using a plurality of circuit elements, such as field effect transistors (FETs), also called metal oxide semiconductor field effect transistors or MOSFETs, occasionally also simply referred to as MOS transistors, and passive elements, such as resistors, e.g., diffusion resistors, and capacitors, integrated on a semiconductor substrate within a given surface area. Typical present-day ICs involve millions of single circuit elements formed on a semiconductor substrate.
The basic function of a MOSFET is that of an electronic switching element, controlling a current through a channel region provided between two junction regions, which are referred to as source and drain. The control of the conductivity state of the channel region is achieved by means of a gate electrode being disposed over the channel region and to which gate electrode a voltage relative to source and drain is applied. In common planar MOSFETs, the channel region extends in a plane between source and drain. Generally, in applying a voltage exceeding a characteristic voltage level to the gate electrode, the conductivity state of the channel is changed and switching between a conducting state or “ON-state” and a non-conducting state or “OFF-state” may be achieved. It is important to note that the characteristic voltage level at which the conductivity state changes (usually called the “threshold voltage”) therefore characterizes the switching behavior of the MOSFET and it is generally an issue to keep variations in the threshold voltage level low when implementing a desired switching characteristic. However, with the threshold voltage depending nontrivially on the transistor's properties, e.g., materials, dimensions, etc., the implementation of a desired threshold voltage value during fabrication processes involves careful adjustment and fine tuning during the fabrication processes, which makes the fabrication of complex semiconductor devices by advanced technologies more and more difficult.
The continued miniaturization of semiconductor devices into the deep submicron regime becomes more and more challenging at vary small scales. One of the several manufacturing strategies employed herein is given by SOI technologies. SOI (silicon-on-insulator) refers to the use of a layered silicon-insulator-silicon substrate in place of conventional silicon substrates in semiconductor manufacturing, especially microelectronics, to reduce parasitic device capacitances and short channel effects, thereby improving performance. Semiconductor devices on the basis of SOI differ from conventional semiconductor devices formed on the bulk substrate in that the silicon junction is formed above an electrical insulator, typically silicon dioxide or sapphire (these types of devices are called “silicon-on-sapphire” or “SOS” devices). The choice of insulator depends largely on the intended application, with sapphire usually being employed in high performance radio frequency applications and radiation sensitive applications, and silicon dioxide providing for diminished short channel effects in microelectronic devices.
Basically, two types of SOI devices are distinguished, that is PDSOI (partially depleted SOI) devices and FDSOI (fully depleted SOI) devices. The PDSOI and FDSOI devices differ by the thickness of a silicon layer which is disposed over a buried oxide layer (also referred to as “BOX layer”, about 145 nm thick—as an “ultra thin BOX” or “UTBOX”, the thickness is in a range from about 10-30 nm), as will be explained with regard to FIG. 1 below. In PDSOI devices, the thickness of the silicon layer is so large that the depletion region formed in the silicon layer does not cover the whole channel region provided in the silicon layer below a gate electrode. Therefore, PDSOI devices behave to a certain extent like bulk semiconductor devices, the more so as the thickness of the silicon layer is increased. The thickness of the silicon layer of conventional PDSOI devices is about 70 nm. FDSOI devices, on the other hand, have a silicon film (conventionally about 5-10 nm thick) formed on the BOX layer or UTBOX layer such that the depletion region in FDSOI devices substantially covers the whole silicon film. Due to the increase in the inversion charges in FDSOI devices, these devices have a higher switching speed. Furthermore, FDSOI devices do not require any doping in the channel region. In general, drawbacks of bulk semiconductor devices, like threshold roll-off, higher sub-threshold slope body effects, short channel effects, etc., are reduced.
A conventional SOI-based semiconductor device 100 is schematically illustrated in FIG. 1. The semiconductor device 100 comprises a gate structure 130 formed over a portion of a semiconductor substrate 110 comprising a silicon film 116, a buried oxide or BOX material 114 and a base silicon 112. The silicon film 116, the BOX material 114 and a portion of the base silicon 112 are surrounded by an insulating structure 120, such as a shallow trench isolation (STI) structure. The insulating structure 120 encompasses an active region of the semiconductor substrate 110 of the SOI type.
From a physical point of view, the silicon film 116 over the BOX material 114 enables the semiconductor material under the gate structure 130, i.e., in the channel region or body of the semiconductor device 100, to be at least partially depleted of charges for PDSOI devices and to be fully depleted of charges in case of FDSOI devices. The net effect is that the gate structure 130 (formed by a gate dielectric 132, a gate electrode 134, a gate contact 136 and sidewall spacers 138) disposed over the semiconductor substrate 110 of the SOI type can now very tightly control the full volume of the body of the semiconductor device 100.
The design process flows and design methodologies to design an FDSOI device, such as the semiconductor device 100, are the same as those normally used in bulk MOS techniques. Basic advantages of FDSOI devices are the lack of a floating body effect or a kink effect associated with PDSOI devices.
However, at very low scales, SOI devices (including FDSOI devices) give rise to very high parasitic capacitances, as will be described below with regard to FIG. 1. Due to the reduced thicknesses of the silicon film 116 in the semiconductor device 100, raised source/drain regions 142 having silicide contacts 144 formed thereon for contacting source/drain contacts 146 are provided, and the raised source/drain regions 142 reduce the resistance of the source/drain contacts in FDSOI devices.
On the other hand, the capacitance of the semiconductor device 100 is increased by the raised source/drain regions 142. Particularly, the raised drain region causes parasitic capacitances between the gate structure 130 and the contact, e.g., a parasitic capacitance C1 (schematically denoting the parasitic gate-contact capacitance), a capacitance C2 (denoting a parasitic capacitance between the gate electrode 134 and the raised drain region, particularly, the raised contact 144), and a parasitic capacitance C3 (originating from a gate overlap). The contribution of the parasitic capacitances C1, C2, C3 to the gate-drain capacitance is at about 61% of the gate capacitance.
From the above description, it is therefore desirable to provide a semiconductor device of SOI type having an improved gate-drain capacitance, while maintaining a low resistance in the contact to source/drain of SOI semiconductor device, particularly with regard to FDSOI devices. It is furthermore desirable to provide for a method of forming an according semiconductor device.